From 8ddc3d0e770c287af88d48d965a377a41b49d44e Mon Sep 17 00:00:00 2001 From: Oliver Ford Date: Wed, 9 Jul 2008 22:50:26 +0100 Subject: [PATCH] Try to use udc driver for u2d --- arch/arm/mach-pxa/hpipaq214.c | 17 + drivers/usb/gadget/Kconfig | 2 +- drivers/usb/gadget/mhn-u2d-regs.h | 152 +++++++++ drivers/usb/gadget/pxa27x_mona_u2d.h | 568 ++++++++++++++++++++++++++++++++++ drivers/usb/gadget/pxa27x_u2d.h | 330 ++++++++++++++++++++ drivers/usb/gadget/pxa27x_u2d_regs.h | 7 + drivers/usb/gadget/pxa27x_udc.c | 409 +++++++++++++------------ 7 files changed, 1286 insertions(+), 199 deletions(-) create mode 100644 drivers/usb/gadget/mhn-u2d-regs.h create mode 100644 drivers/usb/gadget/pxa27x_mona_u2d.h create mode 100644 drivers/usb/gadget/pxa27x_u2d.h create mode 100644 drivers/usb/gadget/pxa27x_u2d_regs.h diff --git a/arch/arm/mach-pxa/hpipaq214.c b/arch/arm/mach-pxa/hpipaq214.c index 1a27f12..715b279 100644 --- a/arch/arm/mach-pxa/hpipaq214.c +++ b/arch/arm/mach-pxa/hpipaq214.c @@ -82,6 +82,7 @@ static struct platform_device hpipaq214_sound_fabric_device = { //Other devices are added by arch/arm/mach-pxa/devices.c because we have a PXA3xx static struct platform_device *hpipaq214_devices[] __initdata = { + &pxa27x_device_udc, //hack n' slash &hpipaq214_pxa2xx_pcm, &hpipaq214_ac97_device, &hpipaq214_wm9713_codec, @@ -548,6 +549,21 @@ static void __init hpipaq214_init_nand(void) static inline void hpipaq214_init_nand(void) {} #endif /* CONFIG_MTD_NAND_PXA3xx || CONFIG_MTD_NAND_PXA3xx_MODULE */ +#ifdef CONFIG_USB_GADGET_PXA2XX +static struct pxa2xx_udc_mach_info hpipaq214_udc_info __initdata = { +// err... +// .gpio_vbus = GPIO_GUMSTIX_USB_GPIOn, +// .gpio_pullup = GPIO_GUMSTIX_USB_GPIOx, +}; + +static void __init hpipaq214_udc_init(void) +{ + pxa_set_udc_info(&hpipaq214_udc_info); +} +#else +static void hpipaq214_udc_init(void){} +#endif + static void __init hpipaq214_init(void) { @@ -557,6 +573,7 @@ static void __init hpipaq214_init(void) hpipaq214_init_mmc(); hpipaq214_init_keypad(); hpipaq214_init_nand(); + hpipaq214_udc_init(); //add the various platform devices platform_add_devices(hpipaq214_devices, ARRAY_SIZE(hpipaq214_devices)); diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 13dcec3..b3bb9bf 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -233,7 +233,7 @@ config SUPERH_BUILT_IN_M66592 config USB_GADGET_PXA27X boolean "PXA 27x" - depends on ARCH_PXA && PXA27x + depends on ARCH_PXA && (PXA27x || PXA3xx) help Intel's PXA 27x series XScale ARM v5TE processors include an integrated full speed USB 1.1 device controller. diff --git a/drivers/usb/gadget/mhn-u2d-regs.h b/drivers/usb/gadget/mhn-u2d-regs.h new file mode 100644 index 0000000..d471c59 --- /dev/null +++ b/drivers/usb/gadget/mhn-u2d-regs.h @@ -0,0 +1,152 @@ +#error scrap, don't use + + +/* USB 2.0 device controller */ +#define U2DCR __REG_3(0x54100000) /* U2D Control Register */ +#define U2DCR_NDC (1 << 31) /* NAK during config */ +#define U2DCR_HSTC_MASK (0x7 << 28) /* High Speed Timeout Calibration */ +#define U2DCR_HSTC_S (28) /* shift */ +#define U2DCR_FSTC_MASK (0x7 << 24) /* Full Speed Timeout Calibration */ +#define U2DCR_FSTC_S (24) /* shift */ +#define U2DCR_UCLKOVR (1 << 22) /* UTM Clock Override */ +#define U2DCR_ABP (1 << 21) /* Application Bus Power */ +#define U2DCR_ADD (1 << 20) /* Application Device Disconnect */ +#define U2DCR_CC (1 << 19) /* Configuration Change */ +#define U2DCR_HS (1 << 18) /* High Speed USB Detection */ +#define U2DCR_SMAC (1 << 17) /* Switch Endpoint Memofy to Actuve Configuration */ +#define U2DCR_DWRE (1 << 16) /* Device Remote Wake-up Feature */ +#define U2DCR_ACN (0xf << 12) /* Active U2D Configuration Number */ +#define U2DCR_ACN_S 12 /* shift */ +#define U2DCR_AIN (0xf << 8) /* Active U2D Interface Number */ +#define U2DCR_AIN_S 8 /* shift */ +#define U2DCR_AAISN (0xf << 4) /* Active U2D Alternate Interface Setting Number */ +#define U2DCR_AAISN_S 4 /* shift */ +#define U2DCR_EMCE (1 << 3) /* Endpoint Memory Configuration Error */ +#define U2DCR_UDR (1 << 2) /* U2D Resume */ +#define U2DCR_UDA (1 << 1) /* U2D Active */ +#define U2DCR_UDE (1 << 0) /* U2D Enable */ +#define U2DCR_MASK_BITS (U2DCR_NDC | U2DCR_ABP | U2DCR_ADD | U2DCR_SMAC | U2DCR_UDR | U2DCR_UDE) + +#define U2DICR __REG_3(0x54100004) /* U2D Interrupt Control Register */ +#define U2DISR __REG_3(0x5410000C) /* U2D Interrupt Status Register */ +#define U2DINT_CC (1 << 31) /* Interrupt - Configuration Change */ +#define U2DINT_SOF (1 << 30) /* Interrupt - SOF */ +#define U2DINT_USOF (1 << 29) /* Interrupt - micro SOF */ +#define U2DINT_RU (1 << 28) /* Interrupt - Resume */ +#define U2DINT_SU (1 << 27) /* Interrupt - Suspend */ +#define U2DINT_RS (1 << 26) /* Interrupt - Reset */ +#define U2DINT_DPE (1 << 25) /* Interrupt - Data Packet Error */ +#define U2DINT_FIFOERR (0x4) /* Interrupt - endpoint FIFO error */ +#define U2DINT_PACKETCMP (0x2) /* Interrupt - endpoint packet complete */ +#define U2DINT_SPACKETCMP (0x1) /* Interrupt - endpoint short packet complete */ +#define U2DINT(n,intr) (((intr) & 0x07) << (((n) & 0x07) * 3)) + +#define U2DFNR __REG_3(0x54100014) /* U2D Frame Number Register */ + +#define U2DCSR0 __REG_3(0x54100100) /* U2D Control/Status Register - Endpoint 0 */ +#define U2DCSR0_IPA (1 << 8) /* IN Packet Adjusted */ +#define U2DCSR0_SA (1 << 7) /* SETUP Active */ +#define U2DCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ +#define U2DCSR0_FST (1 << 5) /* Force Stall */ +#define U2DCSR0_SST (1 << 4) /* Send Stall */ +#define U2DCSR0_DME (1 << 3) /* DMA Enable */ +#define U2DCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ +#define U2DCSR0_IPR (1 << 1) /* IN Packet Ready */ +#define U2DCSR0_OPC (1 << 0) /* OUT Packet Complete */ + +#define U2DCSR(x) __REG_3(0x54100100 + ((x)<<2)) /* U2D Control/Status Register - Endpoint x */ +#define U2DCSR_BF (1 << 10) /* Buffer Full, for OUT eps*/ +#define U2DCSR_BE (1 << 10) /* Buffer Empty, for IN eps */ +#define U2DCSR_DPE (1 << 9) /* Data Packet Error, for ISO eps only */ +#define U2DCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ +#define U2DCSR_SP (1 << 7) /* Short Packet Control/Status, for OUT eps only, readonly */ +#define U2DCSR_BNE (1 << 6) /* Buffer Not Empty, for OUT eps */ +#define U2DCSR_BNF (1 << 6) /* Buffer Not Full, for IN eps */ +#define U2DCSR_FST (1 << 5) /* Force STALL, write 1 set */ +#define U2DCSR_SST (1 << 4) /* Sent STALL, write 1 clear */ +#define U2DCSR_DME (1 << 3) /* DMA Enable */ +#define U2DCSR_TRN (1 << 2) /* Tx/Rx NAK, write 1 clear */ +#define U2DCSR_PC (1 << 1) /* Packet Complete, write 1 clear */ +#define U2DCSR_FS (1 << 0) /* FIFO needs Service */ + +#define U2DBCR0 __REG_3(0x54100200) /* U2D Byte Count Register - Endpoint 0 */ +#define U2DBCR(x) __REG_3(0x54100200 + ((x)<<2)) /* U2D Byte Count Register - Endpoint x */ + +#define U2DDR0 __REG_3(0x54100300) /* U2D Data Register - Endpoint 0 */ + +#define U2DCONF(x) __REG_3(0x54100400 + ((x)<<2)) /* U2D Configuration Register - Endpoint x */ +#define U2DCONF_EE (1 << 0) /* Endpoint Enable */ +#define U2DCONF_BS_MASK (0x3FE) /* Buffer Size, BS*8=FIFO size, max 8184B = 8KB */ +#define U2DCONF_BS_S (1) + +#define U2DSCA __REG_3(0x54100500) /* U2D Setup Command Address */ +#define U2DSCA_VALUE 0x0120 + +#define U2DEN0 __REG_3(0x54100504) /* U2D Endpoint Information Register - Endpoint 0 */ +#define U2DEN(x) __REG_3(0x54100504 + ((x)<<2)) /* U2D Endpoint Information Register - Endpoint x */ + +#define U2DEN_HBW (0x03 << 30) /* Maximum Packet Size */ +#define U2DEN_HWB_S (30) +#define U2DEN_MPS (0x7ff << 19) /* Maximum Packet Size */ +#define U2DEN_MPS_S (19) +#define U2DEN_AISN (0x0f << 15) /* Alternate Interface Number */ +#define U2DEN_AISN_S (15) +#define U2DEN_IN (0x0f << 11) /* Interface Number */ +#define U2DEN_IN_S (11) +#define U2DEN_CN (0x0f << 7) /* Configuration Number */ +#define U2DEN_CN_S (7) +#define U2DEN_ET (0x03 << 5) /* Endpoint Type: */ +#define U2DEN_ET_S (5) +#define U2DEN_ET_INT (0x03 << 5) /* Interrupt */ +#define U2DEN_ET_BULK (0x02 << 5) /* Bulk */ +#define U2DEN_ET_ISO (0x01 << 5) /* Isochronous */ +#define U2DEN_ET_NU (0x00 << 5) /* Not used */ +#define U2DEN_ED (1 << 4) /* Endpoint Direction */ +#define U2DEN_EN (0x0f) /* Endpoint Number */ +#define U2DEN_EN_S (0) + +/* U2DMA registers */ +#define U2DMACSR0 __REG_3(0x54101000) /* U2DMA Control/Status Register - Channel 0 */ +#define U2DMACSR(x) __REG_3(0x54101000 + ((x)<<2)) /* U2DMA Control/Status Register - Channel x */ +#define U2DMACSR_RUN (1 << 31) /* Run Bit (read / write) */ +#define U2DMACSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ +#define U2DMACSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ +#define U2DMACSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ +#define U2DMACSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ +#define U2DMACSR_RASIRQEN (1 << 23) /* Request After Cnannel Stopped Interrupt Enable */ +#define U2DMACSR_MASKRUN (1 << 22) /* Mask Run */ +#define U2DMACSR_SCEMC (3 << 18) /* System Bus Split Completion Error Message Class */ +#define U2DMACSR_SCEMI (0x1f << 13) /* System Bus Split Completion Error Message Index */ +#define U2DMACSR_BUSERRTYPE (7 << 10) /* PX Bus Error Type */ +#define U2DMACSR_EORINTR (1 << 9) /* End Of Receive */ +#define U2DMACSR_REQPEND (1 << 8) /* Request Pending */ +#define U2DMACSR_RASINTR (1 << 4) /* Request After Channel Stopped (read / write 1 clear) */ +#define U2DMACSR_STOPINTR (1 << 3) /* Stop Interrupt (read only) */ +#define U2DMACSR_ENDINTR (1 << 2) /* End Interrupt (read / write 1 clear) */ +#define U2DMACSR_STARTINTR (1 << 1) /* Start Interrupt (read / write 1 clear) */ +#define U2DMACSR_BUSERRINTR (1 << 0) /* Bus Error Interrupt (read / write 1 clear) */ + +#define U2DMACR __REG_3(0x54101080) /* U2DMA Control Register */ +#define U2DMAINT __REG_3(0x541010F0) /* U2DMA Interrupt Register */ + +#define U2DMABR0 __REG_3(0x54101100) /* U2DMA Branch Register - Channel 0 */ +#define U2DMABR(x) __REG_3(0x54101100 + ((x)<<2)) /* U2DMA Branch Register - Channel x */ + +#define U2DMADSC0 __REG_3(0x54101200) /* U2DMA Descriptor Address Register - Channel 0 */ +#define U2DMADSC(x) __REG_3(0x54101200 + ((x)<<4)) /* U2DMA Descriptor Address Register - Channel x */ + +#define U2DMADSC_STOP (1U<<0) + +#define U2DMASRC0 __REG_3(0x54101204) /* U2DMA Source Address Register - Channel 0 */ +#define U2DMASRC(x) __REG_3(0x54101204 + ((x)<<4)) /* U2DMA Source Address Register - Channel x */ +#define U2DMATRG0 __REG_3(0x54101208) /* U2DMA Target Address Register - Channel 0 */ +#define U2DMATRG(x) __REG_3(0x54101208 + ((x)<<4)) /* U2DMA Target Address Register - Channel x */ + +#define U2DMACMD0 __REG_3(0x5410120C) /* U2DMA Command Address Register - Channel 0 */ +#define U2DMACMD(x) __REG_3(0x5410120C + ((x)<<4)) /* U2DMA Command Address Register - Channel x */ + +#define U2DMACMD_XFRDIS (1 << 31) /* Transfer Direction */ +#define U2DMACMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ +#define U2DMACMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ +#define U2DMACMD_PACKCOMP (1 << 13) /* Packet Complete */ +#define U2DMACMD_LEN (0x07ff) /* length mask (max = 2K - 1) */ diff --git a/drivers/usb/gadget/pxa27x_mona_u2d.h b/drivers/usb/gadget/pxa27x_mona_u2d.h new file mode 100644 index 0000000..43bf3df --- /dev/null +++ b/drivers/usb/gadget/pxa27x_mona_u2d.h @@ -0,0 +1,568 @@ +/* + * linux/drivers/usb/gadget/pxa27x_udc.h + * Intel PXA27x on-chip full speed USB device controller + * + * Inspired by original driver by Frank Becker, David Brownell, and others. + * Copyright (C) 2008 Robert Jarzmik + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __LINUX_USB_GADGET_PXA27X_H +#define __LINUX_USB_GADGET_PXA27X_H + +#include +#include +#include + +/* + * Register definitions + */ +/* Offsets */ +#define U2CCR 0x0000 /* UDC Control Register */ +#define U2DICR0 0x0004 /* UDC Interrupt Control Register0 */ +#define U2DICR1 0x0008 /* UDC Interrupt Control Register1 */ +#define U2DISR0 0x000C /* UDC Interrupt Status Register 0 */ +#define U2DISR1 0x0010 /* UDC Interrupt Status Register 1 */ +#define U2DFNR 0x0014 /* UDC Frame Number Register */ + +//NOTUSED define UDCOTGICR 0x0018 /* UDC On-The-Go interrupt control */ +#define UP2OCR 0x0020 /* USB Port 2 Output Control register */ +#define UP3OCR 0x0024 /* USB Port 3 Output Control register */ + +#define UDCCSRn(x) (0x0100 + ((x)<<2)) /* UDC Control/Status register */ +#define UDCBCRn(x) (0x0200 + ((x)<<2)) /* UDC Byte Count Register */ +#define UDCDRn(x) (0x0300 + ((x)<<2)) /* UDC Data Register */ +#define UDCCRn(x) (0x0400 + ((x)<<2)) /* UDC Control Register */ + + +/*****UDCCR*******/ +//Things that matched in both +#define U2DCR_DWRE (1 << 16) /* Device Remote Wake-up Feature */ + +#define U2DCR_ACN (0xf << 12) /* Active U2D Configuration Number */ +#define U2DCR_ACN_S 12 /* shift */ +#define U2DCR_AIN (0xf << 8) /* Active U2D Interface Number */ +#define U2DCR_AIN_S 8 /* shift */ + +#define U2DCR_AAISN (0xf << 4) /* Active U2D Alternate Interface Setting Number */ +#define U2DCR_AAISN_S 4 /* shift */ +#define U2DCR_SMAC (1 << 17) /* Switch Endpoint Memofy to Active Configuration */ +#define U2DCR_EMCE (1 << 3) /* Endpoint Memory Configuration Error */ +#define U2DCR_UDR (1 << 2) /* U2D Resume */ +#define U2DCR_UDA (1 << 1) /* U2D Active */ +#define U2DCR_UDE (1 << 0) /* U2D Enable */ + +//Thing from UDC not in U2D +// define UDCCR_OEN (1 << 31) /* On-the-Go Enable */ +// define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation +// Protocol Port Support */ +// define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol Support */ +// define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol Enable */ + + +//Things from U2D Not implemented in UDC +// #define U2DCR_NDC (1 << 31) /* NAK during config */ +#define U2DCR_HSTC_MASK (0x7 << 28) /* High Speed Timeout Calibration */ +#define U2DCR_HSTC_S (28) /* shift */ +#define U2DCR_FSTC_MASK (0x7 << 24) /* Full Speed Timeout Calibration */ +#define U2DCR_FSTC_S (24) /* shift */ +#define U2DCR_UCLKOVR (1 << 22) /* UTM Clock Override */ +#define U2DCR_ABP (1 << 21) /* Application Bus Power */ +#define U2DCR_ADD (1 << 20) /* Application Device Disconnect */ +#define U2DCR_CC (1 << 19) /* Configuration Change */ +#define U2DCR_HS (1 << 18) /* High Speed USB Detection */ + + +/******UDCICR/UDCISR*******/ +// UDC +// define UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) +// +// define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */ +// define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */ +// define UDCICR1_IERU (1 << 29) /* IntEn - Resume */ +// define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ +// define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ +// define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ +// define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ +// define UDCICR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL) +// +// define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) +// +// define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */ +// define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */ +// define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */ +// define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */ +// define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */ +// define UDCISR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL) + +/***************************/ +// U2D +// define U2DINT_CC (1 << 31) /* Interrupt - Configuration Change */ +// define U2DINT_SOF (1 << 30) /* Interrupt - SOF */ +// +// define U2DINT_USOF (1 << 29) /* Interrupt - micro SOF */ +// +// define U2DINT_RU (1 << 28) /* Interrupt - Resume */ +// define U2DINT_SU (1 << 27) /* Interrupt - Suspend */ +// define U2DINT_RS (1 << 26) /* Interrupt - Reset */ +// define U2DINT_DPE (1 << 25) /* Interrupt - Data Packet Error */ +// define U2DINT_FIFOERR (0x4) /* Interrupt - endpoint FIFO error */ +// define U2DINT_PACKETCMP (0x2) /* Interrupt - endpoint packet complete */ +// define U2DINT_SPACKETCMP (0x1) /* Interrupt - endpoint short packet complete */ +// define U2DINT(n,intr) (((intr) & 0x07) << (((n) & 0x07) * 3)) + + +/***************************/ +//Built +#define U2DICR1_IECC (1 << 31) /* IntEn - Configuration Change */ +#define U2DICR1_IESOF (1 << 30) /* IntEn - Start of Frame */ +#define U2DICR1_IERU (1 << 28) /* IntEn - Resume */ +#define U2DICR1_IESU (1 << 27) /* IntEn - Suspend */ +#define U2DICR1_IERS (1 << 26) /* IntEn - Reset */ +#define U2DICR_FIFOERR (1 << 2) /* FIFO Error interrupt for EP */ +#define U2DICR_PKTCOMPL (1 << 1) /* Packet Complete interrupt for EP */ +#define U2DICR_SPKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ +#define U2DICR_INT_MASK (U2DICR_FIFOERR | U2DICR_PKTCOMPL | U2DICR_SPKTCOMPL) + +#define UDCISR_INT(n, intr) (((intr) & 0x07) << (((n) & 0x07) * 3)) + +#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */ +#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */ +#define UDCISR1_IRRU (1 << 28) /* IntReq - Resume */ +#define UDCISR1_IRSU (1 << 27) /* IntReq - Suspend */ +#define UDCISR1_IRRS (1 << 26) /* IntReq - Reset */ +#define UDCISR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL) + + +/***************************/ +//endpoint status + +#define UDCCSR0_SA (1 << 7) /* Setup Active */ +#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ +#define UDCCSR0_FST (1 << 5) /* Force Stall */ +#define UDCCSR0_SST (1 << 4) /* Sent Stall */ +#define UDCCSR0_DME (1 << 3) /* DMA Enable */ +#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ +#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ +#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ + +#define U2DCSR0_IPA (1 << 8) /* IN Packet Adjusted */ +#define U2DCSR0_SA (1 << 7) /* SETUP Active */ +#define U2DCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ +#define U2DCSR0_FST (1 << 5) /* Force Stall */ +#define U2DCSR0_SST (1 << 4) /* Send Stall */ +#define U2DCSR0_DME (1 << 3) /* DMA Enable */ +#define U2DCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ +#define U2DCSR0_IPR (1 << 1) /* IN Packet Ready */ +#define U2DCSR0_OPC (1 << 0) /* OUT Packet Complete */ + + +#define UDCCSR_DPE (1 << 9) /* Data Packet Error */ +#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ +#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */ +#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */ +#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */ +#define UDCCSR_FST (1 << 5) /* Force STALL */ +#define UDCCSR_SST (1 << 4) /* Sent STALL */ +#define UDCCSR_DME (1 << 3) /* DMA Enable */ +#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */ +#define UDCCSR_PC (1 << 1) /* Packet Complete */ +#define UDCCSR_FS (1 << 0) /* FIFO needs service */ +/***************************/ + + + + + +#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ +#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt + Rising Edge Interrupt Enable */ +#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt + Falling Edge Interrupt Enable */ +#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge + Interrupt Enable */ +#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge + Interrupt Enable */ +#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge + Interrupt Enable */ +#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge + Interrupt Enable */ +#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge + Interrupt Enable */ +#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge + Interrupt Enable */ +#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising + Edge Interrupt Enable */ +#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling + Edge Interrupt Enable */ +#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge + Interrupt Enable */ +#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge + Interrupt Enable */ + +/* Host Port 2 field bits */ +#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */ +#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */ + /* Transceiver enablers */ +#define UP2OCR_DPPDE (1 << 2) /* D+ Pull Down Enable */ +#define UP2OCR_DMPDE (1 << 3) /* D- Pull Down Enable */ +#define UP2OCR_DPPUE (1 << 4) /* D+ Pull Up Enable */ +#define UP2OCR_DMPUE (1 << 5) /* D- Pull Up Enable */ +#define UP2OCR_DPPUBE (1 << 6) /* D+ Pull Up Bypass Enable */ +#define UP2OCR_DMPUBE (1 << 7) /* D- Pull Up Bypass Enable */ +#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */ +#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */ +#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */ +#define UP2OCR_HXS (1 << 16) /* Transceiver Output Select */ +#define UP2OCR_HXOE (1 << 17) /* Transceiver Output Enable */ +#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */ + + +#define UDCCONR_CN (0x03 << 25) /* Configuration Number */ +#define UDCCONR_CN_S 25 +#define UDCCONR_IN (0x07 << 22) /* Interface Number */ +#define UDCCONR_IN_S 22 +#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */ +#define UDCCONR_AISN_S 19 +#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */ +#define UDCCONR_EN_S 15 +#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */ +#define UDCCONR_ET_S 13 +#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */ +#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */ +#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */ +#define UDCCONR_ET_NU (0x00 << 13) /* Not used */ +#define UDCCONR_ED (1 << 12) /* Endpoint Direction */ +#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */ +#define UDCCONR_MPS_S 2 +#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */ +#define UDCCONR_EE (1 << 0) /* Endpoint Enable */ + +#define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_SMAC | UDCCR_UDR | UDCCR_UDE) +#define UDCCSR_WR_MASK (UDCCSR_DME | UDCCSR_FST) +#define UDC_FNR_MASK (0x7ff) +#define UDC_BCR_MASK (0x3ff) + +/* + * UDCCR = UDC Endpoint Configuration Registers + * UDCCSR = UDC Control/Status Register for this EP + * UDCBCR = UDC Byte Count Remaining (contents of OUT fifo) + * UDCDR = UDC Endpoint Data Register (the fifo) + */ +#define ofs_UDCCR(ep) (UDCCRn(ep->idx)) +#define ofs_UDCCSR(ep) (UDCCSRn(ep->idx)) +#define ofs_UDCBCR(ep) (UDCBCRn(ep->idx)) +#define ofs_UDCDR(ep) (UDCDRn(ep->idx)) + +/* Register access macros */ +#define udc_ep_readl(ep, reg) \ + __raw_readl((ep)->dev->regs + ofs_##reg(ep)) +#define udc_ep_writel(ep, reg, value) \ + __raw_writel((value), ep->dev->regs + ofs_##reg(ep)) +#define udc_ep_readb(ep, reg) \ + __raw_readb((ep)->dev->regs + ofs_##reg(ep)) +#define udc_ep_writeb(ep, reg, value) \ + __raw_writeb((value), ep->dev->regs + ofs_##reg(ep)) +#define udc_readl(dev, reg) \ + __raw_readl((dev)->regs + (reg)) +#define udc_writel(udc, reg, value) \ + __raw_writel((value), (udc)->regs + (reg)) + +#define UDCCSR_MASK (UDCCSR_FST | UDCCSR_DME) +#define UDCCISR0_EP_MASK ~0 +#define UDCCISR1_EP_MASK 0xffff +#define UDCCSR0_CTRL_REQ_MASK (UDCCSR0_OPC | UDCCSR0_SA | UDCCSR0_RNE) + +#define EPIDX(ep) (ep->idx) +#define EPADDR(ep) (ep->addr) +#define EPXFERTYPE(ep) (ep->type) +#define EPNAME(ep) (ep->name) +#define is_ep0(ep) (!ep->idx) +#define EPXFERTYPE_is_ISO(ep) (EPXFERTYPE(ep) == USB_ENDPOINT_XFER_ISOC) + +/* + * Endpoint definitions + * + * Once enabled, pxa endpoint configuration is freezed, and cannot change + * unless a reset happens or the udc is disabled. + * Therefore, we must define all pxa potential endpoint definitions needed for + * all gadget and set them up before the udc is enabled. + * + * As the architecture chosen is fully static, meaning the pxa endpoint + * configurations are set up once and for all, we must provide a way to match + * one usb endpoint (usb_ep) to several pxa endpoints. The reason is that gadget + * layer autoconf doesn't choose the usb_ep endpoint on (config, interface, alt) + * criteria, while the pxa architecture requires that. + * + * The solution is to define several pxa endpoints matching one usb_ep. Ex: + * - "ep1-in" matches pxa endpoint EPA (which is an IN ep at addr 1, when + * the udc talks on (config=3, interface=0, alt=0) + * - "ep1-in" matches pxa endpoint EPB (which is an IN ep at addr 1, when + * the udc talks on (config=3, interface=0, alt=1) + * - "ep1-in" matches pxa endpoint EPC (which is an IN ep at addr 1, when + * the udc talks on (config=2, interface=0, alt=0) + * + * We'll define the pxa endpoint by its index (EPA => idx=1, EPB => idx=2, ...) + */ + +/* + * Endpoint definition helpers + */ +#define USB_EP_DEF(addr, bname, dir, type, maxpkt) \ +{ .usb_ep = { .name = bname, .ops = &pxa_ep_ops, .maxpacket = maxpkt, }, \ + .desc = { .bEndpointAddress = addr | (dir ? USB_DIR_IN : 0), \ + .bmAttributes = type, \ + .wMaxPacketSize = maxpkt, }, \ + .dev = &memory \ +} +#define USB_EP_BULK(addr, bname, dir) \ + USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE) +#define USB_EP_ISO(addr, bname, dir) \ + USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE) +#define USB_EP_INT(addr, bname, dir) \ + USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE) +#define USB_EP_IN_BULK(n) USB_EP_BULK(n, "ep" #n "in-bulk", 1) +#define USB_EP_OUT_BULK(n) USB_EP_BULK(n, "ep" #n "out-bulk", 0) +#define USB_EP_IN_ISO(n) USB_EP_ISO(n, "ep" #n "in-iso", 1) +#define USB_EP_OUT_ISO(n) USB_EP_ISO(n, "ep" #n "out-iso", 0) +#define USB_EP_IN_INT(n) USB_EP_INT(n, "ep" #n "in-int", 1) +#define USB_EP_CTRL USB_EP_DEF(0, "ep0", 0, 0, EP0_FIFO_SIZE) + +#define PXA_EP_DEF(_idx, _addr, dir, _type, maxpkt, _config, iface, altset) \ +{ \ + .dev = &memory, \ + .name = "ep" #_idx, \ + .idx = _idx, .enabled = 0, \ + .dir_in = dir, .addr = _addr, \ + .config = _config, .interface = iface, .alternate = altset, \ + .type = _type, .fifo_size = maxpkt, \ +} +#define PXA_EP_BULK(_idx, addr, dir, config, iface, alt) \ + PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE, \ + config, iface, alt) +#define PXA_EP_ISO(_idx, addr, dir, config, iface, alt) \ + PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE, \ + config, iface, alt) +#define PXA_EP_INT(_idx, addr, dir, config, iface, alt) \ + PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE, \ + config, iface, alt) +#define PXA_EP_IN_BULK(i, adr, c, f, a) PXA_EP_BULK(i, adr, 1, c, f, a) +#define PXA_EP_OUT_BULK(i, adr, c, f, a) PXA_EP_BULK(i, adr, 0, c, f, a) +#define PXA_EP_IN_ISO(i, adr, c, f, a) PXA_EP_ISO(i, adr, 1, c, f, a) +#define PXA_EP_OUT_ISO(i, adr, c, f, a) PXA_EP_ISO(i, adr, 0, c, f, a) +#define PXA_EP_IN_INT(i, adr, c, f, a) PXA_EP_INT(i, adr, 1, c, f, a) +#define PXA_EP_CTRL PXA_EP_DEF(0, 0, 0, 0, EP0_FIFO_SIZE, 0, 0, 0) + +struct pxa27x_udc; + +struct stats { + unsigned long in_ops; + unsigned long out_ops; + unsigned long in_bytes; + unsigned long out_bytes; + unsigned long irqs; +}; + +/** + * struct udc_usb_ep - container of each usb_ep structure + * @usb_ep: usb endpoint + * @desc: usb descriptor, especially type and address + * @dev: udc managing this endpoint + * @pxa_ep: matching pxa_ep (cache of find_pxa_ep() call) + */ +struct udc_usb_ep { + struct usb_ep usb_ep; + struct usb_endpoint_descriptor desc; + struct pxa_udc *dev; + struct pxa_ep *pxa_ep; +}; + +/** + * struct pxa_ep - pxa endpoint + * @dev: udc device + * @queue: requests queue + * @lock: lock to pxa_ep data (queues and stats) + * @enabled: true when endpoint enabled (not stopped by gadget layer) + * @idx: endpoint index (1 => epA, 2 => epB, ..., 24 => epX) + * @name: endpoint name (for trace/debug purpose) + * @dir_in: 1 if IN endpoint, 0 if OUT endpoint + * @addr: usb endpoint number + * @config: configuration in which this endpoint is active + * @interface: interface in which this endpoint is active + * @alternate: altsetting in which this endpoitn is active + * @fifo_size: max packet size in the endpoint fifo + * @type: endpoint type (bulk, iso, int, ...) + * @udccsr_value: save register of UDCCSR0 for suspend/resume + * @udccr_value: save register of UDCCR for suspend/resume + * @stats: endpoint statistics + * + * The *PROBLEM* is that pxa's endpoint configuration scheme is both misdesigned + * (cares about config/interface/altsetting, thus placing needless limits on + * device capability) and full of implementation bugs forcing it to be set up + * for use more or less like a pxa255. + * + * As we define the pxa_ep statically, we must guess all needed pxa_ep for all + * gadget which may work with this udc driver. + */ +struct pxa_ep { + struct pxa_udc *dev; + + struct list_head queue; + spinlock_t lock; /* Protects this structure */ + /* (queues, stats) */ + unsigned enabled:1; + + unsigned idx:5; + char *name; + + /* + * Specific pxa endpoint data, needed for hardware initialization + */ + unsigned dir_in:1; + unsigned addr:3; + unsigned config:2; + unsigned interface:3; + unsigned alternate:3; + unsigned fifo_size; + unsigned type; + +#ifdef CONFIG_PM + u32 udccsr_value; + u32 udccr_value; +#endif + struct stats stats; +}; + +/** + * struct pxa27x_request - container of each usb_request structure + * @req: usb request + * @udc_usb_ep: usb endpoint the request was submitted on + * @in_use: sanity check if request already queued on an pxa_ep + * @queue: linked list of requests, linked on pxa_ep->queue + */ +struct pxa27x_request { + struct usb_request req; + struct udc_usb_ep *udc_usb_ep; + unsigned in_use:1; + struct list_head queue; +}; + +enum ep0_state { + WAIT_FOR_SETUP, + SETUP_STAGE, + IN_DATA_STAGE, + OUT_DATA_STAGE, + IN_STATUS_STAGE, + OUT_STATUS_STAGE, + STALL, + WAIT_ACK_SET_CONF_INTERF +}; + +static char *ep0_state_name[] = { + "WAIT_FOR_SETUP", "SETUP_STAGE", "IN_DATA_STAGE", "OUT_DATA_STAGE", + "IN_STATUS_STAGE", "OUT_STATUS_STAGE", "STALL", + "WAIT_ACK_SET_CONF_INTERF" +}; +#define EP0_STNAME(udc) ep0_state_name[(udc)->ep0state] + +#define EP0_FIFO_SIZE 16U +#define BULK_FIFO_SIZE 64U +#define ISO_FIFO_SIZE 256U +#define INT_FIFO_SIZE 16U + +struct udc_stats { + unsigned long irqs_reset; + unsigned long irqs_suspend; + unsigned long irqs_resume; + unsigned long irqs_reconfig; +}; + +#define NR_USB_ENDPOINTS (1 + 5) /* ep0 + ep1in-bulk + .. + ep3in-iso */ +#define NR_PXA_ENDPOINTS (1 + 14) /* ep0 + epA + epB + .. + epX */ + +/** + * struct pxa_udc - udc structure + * @regs: mapped IO space + * @irq: udc irq + * @clk: udc clock + * @usb_gadget: udc gadget structure + * @driver: bound gadget (zero, g_ether, g_file_storage, ...) + * @dev: device + * @mach: machine info, used to activate specific GPIO + * @ep0state: control endpoint state machine state + * @stats: statistics on udc usage + * @udc_usb_ep: array of usb endpoints offered by the gadget + * @pxa_ep: array of pxa available endpoints + * @config: UDC active configuration + * @last_interface: UDC interface of the last SET_INTERFACE host request + * @last_alternate: UDC altsetting of the last SET_INTERFACE host request + * @udccsr0: save of udccsr0 in case of suspend + * @debugfs_root: root entry of debug filesystem + * @debugfs_state: debugfs entry for "udcstate" + * @debugfs_queues: debugfs entry for "queues" + * @debugfs_eps: debugfs entry for "epstate" + */ +struct pxa_udc { + void __iomem *regs; + int irq; + struct clk *clk; + + struct usb_gadget gadget; + struct usb_gadget_driver *driver; + struct device *dev; + struct pxa2xx_udc_mach_info *mach; + + enum ep0_state ep0state; + struct udc_stats stats; + + struct udc_usb_ep udc_usb_ep[NR_USB_ENDPOINTS]; + struct pxa_ep pxa_ep[NR_PXA_ENDPOINTS]; + + unsigned config:2; + unsigned last_interface:3; + unsigned last_alternate:3; + +#ifdef CONFIG_PM + unsigned udccsr0; +#endif +#ifdef CONFIG_USB_GADGET_DEBUG_FS + struct dentry *debugfs_root; + struct dentry *debugfs_state; + struct dentry *debugfs_queues; + struct dentry *debugfs_eps; +#endif +}; + +static inline struct pxa_udc *to_gadget_udc(struct usb_gadget *gadget) +{ + return container_of(gadget, struct pxa_udc, gadget); +} + +/* + * Debugging/message support + */ +#define ep_dbg(ep, fmt, arg...) \ + dev_dbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg) +#define ep_vdbg(ep, fmt, arg...) \ + dev_vdbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg) +#define ep_err(ep, fmt, arg...) \ + dev_err(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg) +#define ep_info(ep, fmt, arg...) \ + dev_info(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg) +#define ep_warn(ep, fmt, arg...) \ + dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg) + +#endif /* __LINUX_USB_GADGET_PXA27X_H */ diff --git a/drivers/usb/gadget/pxa27x_u2d.h b/drivers/usb/gadget/pxa27x_u2d.h new file mode 100644 index 0000000..15a60d7 --- /dev/null +++ b/drivers/usb/gadget/pxa27x_u2d.h @@ -0,0 +1,330 @@ + + +/* + * linux/drivers/usb/gadget/pxa27x_udc.h + * Intel PXA27x on-chip full speed USB device controller + * + * Inspired by original driver by Frank Becker, David Brownell, and others. + * Copyright (C) 2008 Robert Jarzmik + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __LINUX_USB_GADGET_PXA27X_U2D_H +#define __LINUX_USB_GADGET_PXA27X_U2D_H + +#include +#include +#include + +/* + * Register definitions + */ + +/* Register access macros */ +#define udc_ep_readl(ep, reg) \ + __raw_readl((ep)->dev->regs + ofs_##reg(ep)) +#define udc_ep_writel(ep, reg, value) \ + __raw_writel((value), ep->dev->regs + ofs_##reg(ep)) +#define udc_ep_readb(ep, reg) \ + __raw_readb((ep)->dev->regs + ofs_##reg(ep)) +#define udc_ep_writeb(ep, reg, value) \ + __raw_writeb((value), ep->dev->regs + ofs_##reg(ep)) +#define udc_readl(dev, reg) \ + __raw_readl((dev)->regs + (reg)) +#define udc_writel(udc, reg, value) \ + __raw_writel((value), (udc)->regs + (reg)) + + +#define EPIDX(ep) (ep->idx) +#define EPADDR(ep) (ep->addr) +#define EPXFERTYPE(ep) (ep->type) +#define EPNAME(ep) (ep->name) +#define is_ep0(ep) (!ep->idx) +#define EPXFERTYPE_is_ISO(ep) (EPXFERTYPE(ep) == USB_ENDPOINT_XFER_ISOC) + +/* + * Endpoint definitions + * + * Once enabled, pxa endpoint configuration is freezed, and cannot change + * unless a reset happens or the udc is disabled. + * Therefore, we must define all pxa potential endpoint definitions needed for + * all gadget and set them up before the udc is enabled. + * + * As the architecture chosen is fully static, meaning the pxa endpoint + * configurations are set up once and for all, we must provide a way to match + * one usb endpoint (usb_ep) to several pxa endpoints. The reason is that gadget + * layer autoconf doesn't choose the usb_ep endpoint on (config, interface, alt) + * criteria, while the pxa architecture requires that. + * + * The solution is to define several pxa endpoints matching one usb_ep. Ex: + * - "ep1-in" matches pxa endpoint EPA (which is an IN ep at addr 1, when + * the udc talks on (config=3, interface=0, alt=0) + * - "ep1-in" matches pxa endpoint EPB (which is an IN ep at addr 1, when + * the udc talks on (config=3, interface=0, alt=1) + * - "ep1-in" matches pxa endpoint EPC (which is an IN ep at addr 1, when + * the udc talks on (config=2, interface=0, alt=0) + * + * We'll define the pxa endpoint by its index (EPA => idx=1, EPB => idx=2, ...) + */ + +/* + * Endpoint definition helpers + */ +#define USB_EP_DEF(addr, bname, dir, type, maxpkt) \ +{ .usb_ep = { .name = bname, .ops = &pxa_ep_ops, .maxpacket = maxpkt, }, \ + .desc = { .bEndpointAddress = addr | (dir ? USB_DIR_IN : 0), \ + .bmAttributes = type, \ + .wMaxPacketSize = maxpkt, }, \ + .dev = &memory \ +} +#define USB_EP_BULK(addr, bname, dir) \ + USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE) +#define USB_EP_ISO(addr, bname, dir) \ + USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE) +#define USB_EP_INT(addr, bname, dir) \ + USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE) +#define USB_EP_IN_BULK(n) USB_EP_BULK(n, "ep" #n "in-bulk", 1) +#define USB_EP_OUT_BULK(n) USB_EP_BULK(n, "ep" #n "out-bulk", 0) +#define USB_EP_IN_ISO(n) USB_EP_ISO(n, "ep" #n "in-iso", 1) +#define USB_EP_OUT_ISO(n) USB_EP_ISO(n, "ep" #n "out-iso", 0) +#define USB_EP_IN_INT(n) USB_EP_INT(n, "ep" #n "in-int", 1) +#define USB_EP_CTRL USB_EP_DEF(0, "ep0", 0, 0, EP0_FIFO_SIZE) + +#define PXA_EP_DEF(_idx, _addr, dir, _type, maxpkt, _config, iface, altset) \ +{ \ + .dev = &memory, \ + .name = "ep" #_idx, \ + .idx = _idx, .enabled = 0, \ + .dir_in = dir, .addr = _addr, \ + .config = _config, .interface = iface, .alternate = altset, \ + .type = _type, .fifo_size = maxpkt, \ +} +#define PXA_EP_BULK(_idx, addr, dir, config, iface, alt) \ + PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE, \ + config, iface, alt) +#define PXA_EP_ISO(_idx, addr, dir, config, iface, alt) \ + PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE, \ + config, iface, alt) +#define PXA_EP_INT(_idx, addr, dir, config, iface, alt) \ + PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE, \ + config, iface, alt) +#define PXA_EP_IN_BULK(i, adr, c, f, a) PXA_EP_BULK(i, adr, 1, c, f, a) +#define PXA_EP_OUT_BULK(i, adr, c, f, a) PXA_EP_BULK(i, adr, 0, c, f, a) +#define PXA_EP_IN_ISO(i, adr, c, f, a) PXA_EP_ISO(i, adr, 1, c, f, a) +#define PXA_EP_OUT_ISO(i, adr, c, f, a) PXA_EP_ISO(i, adr, 0, c, f, a) +#define PXA_EP_IN_INT(i, adr, c, f, a) PXA_EP_INT(i, adr, 1, c, f, a) +#define PXA_EP_CTRL PXA_EP_DEF(0, 0, 0, 0, EP0_FIFO_SIZE, 0, 0, 0) + +struct pxa27x_udc; + +struct stats { + unsigned long in_ops; + unsigned long out_ops; + unsigned long in_bytes; + unsigned long out_bytes; + unsigned long irqs; +}; + +/** + * struct udc_usb_ep - container of each usb_ep structure + * @usb_ep: usb endpoint + * @desc: usb descriptor, especially type and address + * @dev: udc managing this endpoint + * @pxa_ep: matching pxa_ep (cache of find_pxa_ep() call) + */ +struct udc_usb_ep { + struct usb_ep usb_ep; + struct usb_endpoint_descriptor desc; + struct pxa_udc *dev; + struct pxa_ep *pxa_ep; +}; + +/** + * struct pxa_ep - pxa endpoint + * @dev: udc device + * @queue: requests queue + * @lock: lock to pxa_ep data (queues and stats) + * @enabled: true when endpoint enabled (not stopped by gadget layer) + * @idx: endpoint index (1 => epA, 2 => epB, ..., 24 => epX) + * @name: endpoint name (for trace/debug purpose) + * @dir_in: 1 if IN endpoint, 0 if OUT endpoint + * @addr: usb endpoint number + * @config: configuration in which this endpoint is active + * @interface: interface in which this endpoint is active + * @alternate: altsetting in which this endpoitn is active + * @fifo_size: max packet size in the endpoint fifo + * @type: endpoint type (bulk, iso, int, ...) + * @udccsr_value: save register of UDCCSR0 for suspend/resume + * @udccr_value: save register of UDCCR for suspend/resume + * @stats: endpoint statistics + * + * The *PROBLEM* is that pxa's endpoint configuration scheme is both misdesigned + * (cares about config/interface/altsetting, thus placing needless limits on + * device capability) and full of implementation bugs forcing it to be set up + * for use more or less like a pxa255. + * + * As we define the pxa_ep statically, we must guess all needed pxa_ep for all + * gadget which may work with this udc driver. + */ +struct pxa_ep { + struct pxa_udc *dev; + + struct list_head queue; + spinlock_t lock; /* Protects this structure */ + /* (queues, stats) */ + unsigned enabled:1; + + unsigned idx:5; + char *name; + + /* + * Specific pxa endpoint data, needed for hardware initialization + */ + unsigned dir_in:1; + unsigned addr:3; + unsigned config:2; + unsigned interface:3; + unsigned alternate:3; + unsigned fifo_size; + unsigned type; + +#ifdef CONFIG_PM + u32 udccsr_value; + u32 udccr_value; +#endif + struct stats stats; +}; + +/** + * struct pxa27x_request - container of each usb_request structure + * @req: usb request + * @udc_usb_ep: usb endpoint the request was submitted on + * @in_use: sanity check if request already queued on an pxa_ep + * @queue: linked list of requests, linked on pxa_ep->queue + */ +struct pxa27x_request { + struct usb_request req; + struct udc_usb_ep *udc_usb_ep; + unsigned in_use:1; + struct list_head queue; +}; + +enum ep0_state { + WAIT_FOR_SETUP, + SETUP_STAGE, + IN_DATA_STAGE, + OUT_DATA_STAGE, + IN_STATUS_STAGE, + OUT_STATUS_STAGE, + STALL, + WAIT_ACK_SET_CONF_INTERF +}; + +static char *ep0_state_name[] = { + "WAIT_FOR_SETUP", "SETUP_STAGE", "IN_DATA_STAGE", "OUT_DATA_STAGE", + "IN_STATUS_STAGE", "OUT_STATUS_STAGE", "STALL", + "WAIT_ACK_SET_CONF_INTERF" +}; +#define EP0_STNAME(udc) ep0_state_name[(udc)->ep0state] + +#define EP0_FIFO_SIZE 16U +#define BULK_FIFO_SIZE 64U +#define ISO_FIFO_SIZE 256U +#define INT_FIFO_SIZE 16U + +struct udc_stats { + unsigned long irqs_reset; + unsigned long irqs_suspend; + unsigned long irqs_resume; + unsigned long irqs_reconfig; +}; + +#define NR_USB_ENDPOINTS (1 + 5) /* ep0 + ep1in-bulk + .. + ep3in-iso */ +#define NR_PXA_ENDPOINTS (1 + 14) /* ep0 + epA + epB + .. + epX */ + +/** + * struct pxa_udc - udc structure + * @regs: mapped IO space + * @irq: udc irq + * @clk: udc clock + * @usb_gadget: udc gadget structure + * @driver: bound gadget (zero, g_ether, g_file_storage, ...) + * @dev: device + * @mach: machine info, used to activate specific GPIO + * @ep0state: control endpoint state machine state + * @stats: statistics on udc usage + * @udc_usb_ep: array of usb endpoints offered by the gadget + * @pxa_ep: array of pxa available endpoints + * @config: UDC active configuration + * @last_interface: UDC interface of the last SET_INTERFACE host request + * @last_alternate: UDC altsetting of the last SET_INTERFACE host request + * @udccsr0: save of udccsr0 in case of suspend + * @debugfs_root: root entry of debug filesystem + * @debugfs_state: debugfs entry for "udcstate" + * @debugfs_queues: debugfs entry for "queues" + * @debugfs_eps: debugfs entry for "epstate" + */ +struct pxa_udc { + void __iomem *regs; + int irq; + struct clk *clk; + + struct usb_gadget gadget; + struct usb_gadget_driver *driver; + struct device *dev; + struct pxa2xx_udc_mach_info *mach; + + enum ep0_state ep0state; + struct udc_stats stats; + + struct udc_usb_ep udc_usb_ep[NR_USB_ENDPOINTS]; + struct pxa_ep pxa_ep[NR_PXA_ENDPOINTS]; + + unsigned config:2; + unsigned last_interface:3; + unsigned last_alternate:3; + +#ifdef CONFIG_PM + unsigned udccsr0; +#endif +#ifdef CONFIG_USB_GADGET_DEBUG_FS + struct dentry *debugfs_root; + struct dentry *debugfs_state; + struct dentry *debugfs_queues; + struct dentry *debugfs_eps; +#endif +}; + +static inline struct pxa_udc *to_gadget_udc(struct usb_gadget *gadget) +{ + return container_of(gadget, struct pxa_udc, gadget); +} + +/* + * Debugging/message support + */ +#define ep_dbg(ep, fmt, arg...) \ + dev_dbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg) +#define ep_vdbg(ep, fmt, arg...) \ + dev_vdbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg) +#define ep_err(ep, fmt, arg...) \ + dev_err(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg) +#define ep_info(ep, fmt, arg...) \ + dev_info(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg) +#define ep_warn(ep, fmt, arg...) \ + dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg) + +#endif // __LINUX_USB_GADGET_PXA27X_U2D_H \ No newline at end of file diff --git a/drivers/usb/gadget/pxa27x_u2d_regs.h b/drivers/usb/gadget/pxa27x_u2d_regs.h new file mode 100644 index 0000000..e10ccfa --- /dev/null +++ b/drivers/usb/gadget/pxa27x_u2d_regs.h @@ -0,0 +1,7 @@ + + +#ifndef __LINUX_USB_GADGET_PXA27X_U2D_H +#define __LINUX_USB_GADGET_PXA27X_U2D_H + + +#endif // __LINUX_USB_GADGET_PXA27X_U2D_H \ No newline at end of file diff --git a/drivers/usb/gadget/pxa27x_udc.c b/drivers/usb/gadget/pxa27x_udc.c index 9c0e82e..5b50072 100644 --- a/drivers/usb/gadget/pxa27x_udc.c +++ b/drivers/usb/gadget/pxa27x_udc.c @@ -1,5 +1,5 @@ /* - * Handles the Intel 27x USB Device Controller (UDC) + * Handles the Intel 27x USB Device Controller (U2D) * * Inspired by original driver by Frank Becker, David Brownell, and others. * Copyright (C) 2008 Robert Jarzmik @@ -18,6 +18,9 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * + * ** Converted to run U2D regs area on Monahans LV ** + * The 4060000 U2D area doesn't seem to do anything + * */ #include #include @@ -38,13 +41,13 @@ #include #include #include -#include /* FIXME: for PSSR */ +//include /* FIXME: for PSSR */ #include -#include "pxa27x_udc.h" +#include "pxa27x_u2d.h" /* - * This driver handles the USB Device Controller (UDC) in Intel's PXA 27x + * This driver handles the USB Device Controller (U2D) in Intel's PXA 27x * series processors. * * Such controller drivers work with a gadget driver. The gadget driver @@ -53,7 +56,7 @@ * the different protocol interfaces. The controller driver virtualizes * usb hardware so that the gadget drivers will be more portable. * - * This UDC hardware wants to implement a bit too much USB protocol. The + * This U2D hardware wants to implement a bit too much USB protocol. The * biggest issues are: that the endpoints have to be set up before the * controller can be enabled (minor, and not uncommon); and each endpoint * can only have one configuration, interface and alternative interface @@ -72,7 +75,7 @@ * - ether gadget * * The driver doesn't use DMA, only IO access and IRQ callbacks. No use is - * made of UDC's double buffering either. USB "On-The-Go" is not implemented. + * made of U2D's double buffering either. USB "On-The-Go" is not implemented. * * All the requests are handled the same way : * - the drivers tries to handle the request directly to the IO @@ -113,29 +116,32 @@ static int state_dbg_show(struct seq_file *s, void *p) driver_name, DRIVER_VERSION, udc->driver ? udc->driver->driver.name : "(none)"); - tmp = udc_readl(udc, UDCCR); + tmp = udc_readl(udc, U2DCR); pos += seq_printf(s, - "udccr=0x%0x(%s%s%s%s%s%s%s%s%s%s), " +// "udccr=0x%0x(%s%s%s%s%s%s%s%s%s%s), " + "udccr=0x%0x(%s%s%s%s%s%s), " "con=%d,inter=%d,altinter=%d\n", tmp, - (tmp & UDCCR_OEN) ? " oen":"", - (tmp & UDCCR_AALTHNP) ? " aalthnp":"", - (tmp & UDCCR_AHNP) ? " rem" : "", - (tmp & UDCCR_BHNP) ? " rstir" : "", - (tmp & UDCCR_DWRE) ? " dwre" : "", - (tmp & UDCCR_SMAC) ? " smac" : "", - (tmp & UDCCR_EMCE) ? " emce" : "", - (tmp & UDCCR_UDR) ? " udr" : "", - (tmp & UDCCR_UDA) ? " uda" : "", - (tmp & UDCCR_UDE) ? " ude" : "", - (tmp & UDCCR_ACN) >> UDCCR_ACN_S, - (tmp & UDCCR_AIN) >> UDCCR_AIN_S, - (tmp & UDCCR_AAISN) >> UDCCR_AAISN_S); +// (tmp & U2DCR_OEN) ? " oen":"", +// (tmp & U2DCR_AALTHNP) ? " aalthnp":"", +// (tmp & U2DCR_AHNP) ? " rem" : "", +// (tmp & U2DCR_BHNP) ? " rstir" : "", + (tmp & U2DCR_DWRE) ? " dwre" : "", + (tmp & U2DCR_SMAC) ? " smac" : "", + (tmp & U2DCR_EMCE) ? " emce" : "", + (tmp & U2DCR_UDR) ? " udr" : "", + (tmp & U2DCR_UDA) ? " uda" : "", + (tmp & U2DCR_UDE) ? " ude" : "", + (tmp & U2DCR_ACN) >> U2DCR_ACN_S, + (tmp & U2DCR_AIN) >> U2DCR_AIN_S, + (tmp & U2DCR_AAISN) >> U2DCR_AAISN_S); + + /* registers for device and ep0 */ pos += seq_printf(s, "udcicr0=0x%08x udcicr1=0x%08x\n", - udc_readl(udc, UDCICR0), udc_readl(udc, UDCICR1)); + udc_readl(udc, U2DICR0), udc_readl(udc, U2DICR1)); pos += seq_printf(s, "udcisr0=0x%08x udcisr1=0x%08x\n", - udc_readl(udc, UDCISR0), udc_readl(udc, UDCISR1)); - pos += seq_printf(s, "udcfnr=%d\n", udc_readl(udc, UDCFNR)); + udc_readl(udc, U2DISR0), udc_readl(udc, U2DISR1)); + pos += seq_printf(s, "udcfnr=%d\n", udc_readl(udc, U2DFNR)); pos += seq_printf(s, "irqs: reset=%lu, suspend=%lu, resume=%lu, " "reconfig=%lu\n", udc->stats.irqs_reset, udc->stats.irqs_suspend, @@ -193,18 +199,18 @@ static int eps_dbg_show(struct seq_file *s, void *p) goto out; ep = &udc->pxa_ep[0]; - tmp = udc_ep_readl(ep, UDCCSR); + tmp = udc_ep_readl(ep, U2DCSR); pos += seq_printf(s, "udccsr0=0x%03x(%s%s%s%s%s%s%s)\n", tmp, - (tmp & UDCCSR0_SA) ? " sa" : "", - (tmp & UDCCSR0_RNE) ? " rne" : "", - (tmp & UDCCSR0_FST) ? " fst" : "", - (tmp & UDCCSR0_SST) ? " sst" : "", - (tmp & UDCCSR0_DME) ? " dme" : "", - (tmp & UDCCSR0_IPR) ? " ipr" : "", - (tmp & UDCCSR0_OPC) ? " opc" : ""); + (tmp & U2DCSR0_SA) ? " sa" : "", + (tmp & U2DCSR0_RNE) ? " rne" : "", + (tmp & U2DCSR0_FST) ? " fst" : "", + (tmp & U2DCSR0_SST) ? " sst" : "", + (tmp & U2DCSR0_DME) ? " dme" : "", + (tmp & U2DCSR0_IPR) ? " ipr" : "", + (tmp & U2DCSR0_OPC) ? " opc" : ""); for (i = 0; i < NR_PXA_ENDPOINTS; i++) { ep = &udc->pxa_ep[i]; - tmp = i? udc_ep_readl(ep, UDCCR) : udc_readl(udc, UDCCR); + tmp = i? udc_ep_readl(ep, U2DCR) : udc_readl(udc, U2DCR); pos += seq_printf(s, "%-12s: " "IN %lu(%lu reqs), OUT %lu(%lu reqs), " "irqs=%lu, udccr=0x%08x, udccsr=0x%03x, " @@ -213,8 +219,8 @@ static int eps_dbg_show(struct seq_file *s, void *p) ep->stats.in_bytes, ep->stats.in_ops, ep->stats.out_bytes, ep->stats.out_ops, ep->stats.irqs, - tmp, udc_ep_readl(ep, UDCCSR), - udc_ep_readl(ep, UDCBCR)); + tmp, udc_ep_readl(ep, U2DCSR), + udc_ep_readl(ep, U2DBCR)); } ret = 0; @@ -358,7 +364,7 @@ static int is_match_usb_pxa(struct udc_usb_ep *udc_usb_ep, struct pxa_ep *ep, * configuration events up to gadget drivers (like all control messages). * * Note that there is still a blurred point here : - * - we rely on UDCCR register "active interface" and "active altsetting". + * - we rely on U2DCR register "active interface" and "active altsetting". * This is a nonsense in regard of USB spec, where multiple interfaces are * active at the same time. * - if we knew for sure that the pxa can handle multiple interface at the @@ -419,13 +425,13 @@ static void pio_irq_enable(struct pxa_ep *ep) { struct pxa_udc *udc = ep->dev; int index = EPIDX(ep); - u32 udcicr0 = udc_readl(udc, UDCICR0); - u32 udcicr1 = udc_readl(udc, UDCICR1); + u32 udcicr0 = udc_readl(udc, U2DICR0); + u32 udcicr1 = udc_readl(udc, U2DICR1); if (index < 16) - udc_writel(udc, UDCICR0, udcicr0 | (3 << (index * 2))); + udc_writel(udc, U2DICR0, udcicr0 | (3 << (index * 2))); else - udc_writel(udc, UDCICR1, udcicr1 | (3 << ((index - 16) * 2))); + udc_writel(udc, U2DICR1, udcicr1 | (3 << ((index - 16) * 2))); } /** @@ -437,41 +443,41 @@ static void pio_irq_disable(struct pxa_ep *ep) { struct pxa_udc *udc = ep->dev; int index = EPIDX(ep); - u32 udcicr0 = udc_readl(udc, UDCICR0); - u32 udcicr1 = udc_readl(udc, UDCICR1); + u32 udcicr0 = udc_readl(udc, U2DICR0); + u32 udcicr1 = udc_readl(udc, U2DICR1); if (index < 16) - udc_writel(udc, UDCICR0, udcicr0 & ~(3 << (index * 2))); + udc_writel(udc, U2DICR0, udcicr0 & ~(3 << (index * 2))); else - udc_writel(udc, UDCICR1, udcicr1 & ~(3 << ((index - 16) * 2))); + udc_writel(udc, U2DICR1, udcicr1 & ~(3 << ((index - 16) * 2))); } /** - * udc_set_mask_UDCCR - set bits in UDCCR + * udc_set_mask_U2DCR - set bits in U2DCR * @udc: udc device - * @mask: bits to set in UDCCR + * @mask: bits to set in U2DCR * - * Sets bits in UDCCR, leaving DME and FST bits as they were. + * Sets bits in U2DCR, leaving DME and FST bits as they were. */ -static inline void udc_set_mask_UDCCR(struct pxa_udc *udc, int mask) +static inline void udc_set_mask_U2DCR(struct pxa_udc *udc, int mask) { - u32 udccr = udc_readl(udc, UDCCR); - udc_writel(udc, UDCCR, - (udccr & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS)); + u32 udccr = udc_readl(udc, U2DCR); + udc_writel(udc, U2DCR, + (udccr & U2DCR_MASK_BITS) | (mask & U2DCR_MASK_BITS)); } /** - * udc_clear_mask_UDCCR - clears bits in UDCCR + * udc_clear_mask_U2DCR - clears bits in U2DCR * @udc: udc device - * @mask: bit to clear in UDCCR + * @mask: bit to clear in U2DCR * - * Clears bits in UDCCR, leaving DME and FST bits as they were. + * Clears bits in U2DCR, leaving DME and FST bits as they were. */ -static inline void udc_clear_mask_UDCCR(struct pxa_udc *udc, int mask) +static inline void udc_clear_mask_U2DCR(struct pxa_udc *udc, int mask) { - u32 udccr = udc_readl(udc, UDCCR); - udc_writel(udc, UDCCR, - (udccr & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS)); + u32 udccr = udc_readl(udc, U2DCR); + udc_writel(udc, U2DCR, + (udccr & U2DCR_MASK_BITS) & ~(mask & U2DCR_MASK_BITS)); } /** @@ -484,7 +490,7 @@ static int ep_count_bytes_remain(struct pxa_ep *ep) { if (ep->dir_in) return -EOPNOTSUPP; - return udc_ep_readl(ep, UDCBCR) & 0x3ff; + return udc_ep_readl(ep, U2DBCR) & 0x3ff; } /** @@ -504,9 +510,9 @@ static int ep_is_empty(struct pxa_ep *ep) if (!is_ep0(ep) && ep->dir_in) return -EOPNOTSUPP; if (is_ep0(ep)) - ret = !(udc_ep_readl(ep, UDCCSR) & UDCCSR0_RNE); + ret = !(udc_ep_readl(ep, U2DCSR) & U2DCSR0_RNE); else - ret = !(udc_ep_readl(ep, UDCCSR) & UDCCSR_BNE); + ret = !(udc_ep_readl(ep, U2DCSR) & U2DCSR_BNE); return ret; } @@ -522,10 +528,10 @@ static int ep_is_empty(struct pxa_ep *ep) static int ep_is_full(struct pxa_ep *ep) { if (is_ep0(ep)) - return (udc_ep_readl(ep, UDCCSR) & UDCCSR0_IPR); + return (udc_ep_readl(ep, U2DCSR) & U2DCSR0_IPR); if (!ep->dir_in) return -EOPNOTSUPP; - return (!(udc_ep_readl(ep, UDCCSR) & UDCCSR_BNF)); + return (!(udc_ep_readl(ep, U2DCSR) & U2DCSR_BNF)); } /** @@ -539,8 +545,8 @@ static int epout_has_pkt(struct pxa_ep *ep) if (!is_ep0(ep) && ep->dir_in) return -EOPNOTSUPP; if (is_ep0(ep)) - return (udc_ep_readl(ep, UDCCSR) & UDCCSR0_OPC); - return (udc_ep_readl(ep, UDCCSR) & UDCCSR_PC); + return (udc_ep_readl(ep, U2DCSR) & U2DCSR0_OPC); + return (udc_ep_readl(ep, U2DCSR) & U2DCSR_PC); } /** @@ -555,8 +561,8 @@ static void set_ep0state(struct pxa_udc *udc, int state) udc->ep0state = state; ep_dbg(ep, "state=%s->%s, udccsr0=0x%03x, udcbcr=%d\n", old_stname, - EP0_STNAME(udc), udc_ep_readl(ep, UDCCSR), - udc_ep_readl(ep, UDCBCR)); + EP0_STNAME(udc), udc_ep_readl(ep, U2DCSR), + udc_ep_readl(ep, U2DBCR)); } /** @@ -602,22 +608,22 @@ static void inc_ep_stats_bytes(struct pxa_ep *ep, int count, int is_in) * pxa_ep_setup - Sets up an usb physical endpoint * @ep: pxa27x physical endpoint * - * Find the physical pxa27x ep, and setup its UDCCR + * Find the physical pxa27x ep, and setup its U2DCR */ static __init void pxa_ep_setup(struct pxa_ep *ep) { u32 new_udccr; - new_udccr = ((ep->config << UDCCONR_CN_S) & UDCCONR_CN) - | ((ep->interface << UDCCONR_IN_S) & UDCCONR_IN) - | ((ep->alternate << UDCCONR_AISN_S) & UDCCONR_AISN) - | ((EPADDR(ep) << UDCCONR_EN_S) & UDCCONR_EN) - | ((EPXFERTYPE(ep) << UDCCONR_ET_S) & UDCCONR_ET) - | ((ep->dir_in) ? UDCCONR_ED : 0) - | ((ep->fifo_size << UDCCONR_MPS_S) & UDCCONR_MPS) - | UDCCONR_EE; + new_udccr = ((ep->config << U2DCONR_CN_S) & U2DCONR_CN) + | ((ep->interface << U2DCONR_IN_S) & U2DCONR_IN) + | ((ep->alternate << U2DCONR_AISN_S) & U2DCONR_AISN) + | ((EPADDR(ep) << U2DCONR_EN_S) & U2DCONR_EN) + | ((EPXFERTYPE(ep) << U2DCONR_ET_S) & U2DCONR_ET) + | ((ep->dir_in) ? U2DCONR_ED : 0) + | ((ep->fifo_size << U2DCONR_MPS_S) & U2DCONR_MPS) + | U2DCONR_EE; - udc_ep_writel(ep, UDCCR, new_udccr); + udc_ep_writel(ep, U2DCR, new_udccr); } /** @@ -692,7 +698,7 @@ static void ep_add_request(struct pxa_ep *ep, struct pxa27x_request *req) if (unlikely(!req)) return; ep_vdbg(ep, "req:%p, lg=%d, udccsr=0x%03x\n", req, - req->req.length, udc_ep_readl(ep, UDCCSR)); + req->req.length, udc_ep_readl(ep, U2DCSR)); req->in_use = 1; list_add_tail(&req->queue, &ep->queue); @@ -715,7 +721,7 @@ static void ep_del_request(struct pxa_ep *ep, struct pxa27x_request *req) if (unlikely(!req)) return; ep_vdbg(ep, "req:%p, lg=%d, udccsr=0x%03x\n", req, - req->req.length, udc_ep_readl(ep, UDCCSR)); + req->req.length, udc_ep_readl(ep, U2DCSR)); list_del_init(&req->queue); req->in_use = 0; @@ -862,10 +868,10 @@ static int read_packet(struct pxa_ep *ep, struct pxa27x_request *req) count = 0; for (i = count; i > 0; i -= 4) - *buf++ = udc_ep_readl(ep, UDCDR); + *buf++ = udc_ep_readl(ep, U2DDR); req->req.actual += count; - udc_ep_writel(ep, UDCCSR, UDCCSR_PC); + udc_ep_writel(ep, U2DCSR, U2DCSR_PC); return count; } @@ -898,14 +904,14 @@ static int write_packet(struct pxa_ep *ep, struct pxa27x_request *req, remain = length & 0x3; count = length & ~(0x3); for (i = count; i > 0 ; i -= 4) - udc_ep_writel(ep, UDCDR, *buf++); + udc_ep_writel(ep, U2DDR, *buf++); buf_8 = (u8 *)buf; for (i = remain; i > 0; i--) - udc_ep_writeb(ep, UDCDR, *buf_8++); + udc_ep_writeb(ep, U2DDR, *buf_8++); ep_vdbg(ep, "length=%d+%d, udccsr=0x%03x\n", count, remain, - udc_ep_readl(ep, UDCCSR)); + udc_ep_readl(ep, U2DCSR)); return length; } @@ -934,7 +940,7 @@ static int read_fifo(struct pxa_ep *ep, struct pxa27x_request *req) is_short = (count < ep->fifo_size); ep_dbg(ep, "read udccsr:%03x, count:%d bytes%s req %p %d/%d\n", - udc_ep_readl(ep, UDCCSR), count, is_short ? "/S" : "", + udc_ep_readl(ep, U2DCSR), count, is_short ? "/S" : "", &req->req, req->req.actual, req->req.length); /* completion */ @@ -969,16 +975,16 @@ static int write_fifo(struct pxa_ep *ep, struct pxa27x_request *req) do { is_short = 0; - udccsr = udc_ep_readl(ep, UDCCSR); - if (udccsr & UDCCSR_PC) { + udccsr = udc_ep_readl(ep, U2DCSR); + if (udccsr & U2DCSR_PC) { ep_vdbg(ep, "Clearing Transmit Complete, udccsr=%x\n", udccsr); - udc_ep_writel(ep, UDCCSR, UDCCSR_PC); + udc_ep_writel(ep, U2DCSR, U2DCSR_PC); } - if (udccsr & UDCCSR_TRN) { + if (udccsr & U2DCSR_TRN) { ep_vdbg(ep, "Clearing Underrun on, udccsr=%x\n", udccsr); - udc_ep_writel(ep, UDCCSR, UDCCSR_TRN); + udc_ep_writel(ep, U2DCSR, U2DCSR_TRN); } count = write_packet(ep, req, max); @@ -1000,7 +1006,7 @@ static int write_fifo(struct pxa_ep *ep, struct pxa27x_request *req) } if (is_short) - udc_ep_writel(ep, UDCCSR, UDCCSR_SP); + udc_ep_writel(ep, U2DCSR, U2DCSR_SP); /* requests complete when all IN data is in the FIFO */ if (is_last) { @@ -1033,12 +1039,12 @@ static int read_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req) while (epout_has_pkt(ep)) { count = read_packet(ep, req); - udc_ep_writel(ep, UDCCSR, UDCCSR0_OPC); + udc_ep_writel(ep, U2DCSR, U2DCSR0_OPC); inc_ep_stats_bytes(ep, count, !USB_DIR_IN); is_short = (count < ep->fifo_size); ep_dbg(ep, "read udccsr:%03x, count:%d bytes%s req %p %d/%d\n", - udc_ep_readl(ep, UDCCSR), count, is_short ? "/S" : "", + udc_ep_readl(ep, U2DCSR), count, is_short ? "/S" : "", &req->req, req->req.actual, req->req.length); if (is_short || req->req.actual >= req->req.length) { @@ -1078,12 +1084,12 @@ static int write_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req) /* Sends either a short packet or a 0 length packet */ if (unlikely(is_short)) - udc_ep_writel(ep, UDCCSR, UDCCSR0_IPR); + udc_ep_writel(ep, U2DCSR, U2DCSR0_IPR); ep_dbg(ep, "in %d bytes%s%s, %d left, req=%p, udccsr0=0x%03x\n", count, is_short ? "/S" : "", is_last ? "/L" : "", req->req.length - req->req.actual, - &req->req, udc_ep_readl(ep, UDCCSR)); + &req->req, udc_ep_readl(ep, U2DCSR)); return is_last; } @@ -1270,7 +1276,7 @@ static int pxa_ep_set_halt(struct usb_ep *_ep, int value) /* * This path (reset toggle+halt) is needed to implement * SET_INTERFACE on normal hardware. but it can't be - * done from software on the PXA UDC, and the hardware + * done from software on the PXA U2D, and the hardware * forgets to do it as part of SET_INTERFACE automagic. */ ep_dbg(ep, "only host can clear halt\n"); @@ -1285,7 +1291,7 @@ static int pxa_ep_set_halt(struct usb_ep *_ep, int value) /* FST, FEF bits are the same for control and non control endpoints */ rc = 0; - udc_ep_writel(ep, UDCCSR, UDCCSR_FST | UDCCSR_FEF); + udc_ep_writel(ep, U2DCSR, U2DCSR_FST | U2DCSR_FEF); if (is_ep0(ep)) set_ep0state(ep->dev, STALL); @@ -1348,12 +1354,12 @@ static void pxa_ep_fifo_flush(struct usb_ep *_ep) /* for OUT, just read and discard the FIFO contents. */ if (!ep->dir_in) { while (!ep_is_empty(ep)) - udc_ep_readl(ep, UDCDR); + udc_ep_readl(ep, U2DDR); } else { /* most IN status is the same, but ISO can't stall */ - udc_ep_writel(ep, UDCCSR, - UDCCSR_PC | UDCCSR_FEF | UDCCSR_TRN - | (EPXFERTYPE_is_ISO(ep) ? 0 : UDCCSR_SST)); + udc_ep_writel(ep, U2DCSR, + U2DCSR_PC | U2DCSR_FEF | U2DCSR_TRN + | (EPXFERTYPE_is_ISO(ep) ? 0 : U2DCSR_SST)); } spin_unlock_irqrestore(&ep->lock, flags); @@ -1483,7 +1489,7 @@ static int pxa_udc_get_frame(struct usb_gadget *_gadget) { struct pxa_udc *udc = to_gadget_udc(_gadget); - return (udc_readl(udc, UDCFNR) & 0x7ff); + return (udc_readl(udc, U2DFNR) & 0x7ff); } /** @@ -1497,9 +1503,9 @@ static int pxa_udc_wakeup(struct usb_gadget *_gadget) struct pxa_udc *udc = to_gadget_udc(_gadget); /* host may not have enabled remote wakeup */ - if ((udc_readl(udc, UDCCR) & UDCCR_DWRE) == 0) + if ((udc_readl(udc, U2DCR) & U2DCR_DWRE) == 0) return -EHOSTUNREACH; - udc_set_mask_UDCCR(udc, UDCCR_UDR); + udc_set_mask_U2DCR(udc, U2DCR_UDR); return 0; } @@ -1518,16 +1524,16 @@ static const struct usb_gadget_ops pxa_udc_ops = { */ static void udc_disable(struct pxa_udc *udc) { - udc_writel(udc, UDCICR0, 0); - udc_writel(udc, UDCICR1, 0); + udc_writel(udc, U2DICR0, 0); + udc_writel(udc, U2DICR1, 0); - udc_clear_mask_UDCCR(udc, UDCCR_UDE); + udc_clear_mask_U2DCR(udc, U2DCR_UDE); clk_disable(udc->clk); ep0_idle(udc); udc->gadget.speed = USB_SPEED_UNKNOWN; if (udc->mach->udc_command) - udc->mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT); + udc->mach->udc_command(PXA2XX_U2D_CMD_DISCONNECT); } /** @@ -1569,14 +1575,14 @@ static __init void udc_init_data(struct pxa_udc *dev) * @dev: udc device * * Enables the udc device : enables clocks, udc interrupts, control endpoint - * interrupts, sets usb as UDC client and setups endpoints. + * interrupts, sets usb as U2D client and setups endpoints. */ static void udc_enable(struct pxa_udc *udc) { - udc_writel(udc, UDCICR0, 0); - udc_writel(udc, UDCICR1, 0); - udc_writel(udc, UP2OCR, UP2OCR_HXOE); - udc_clear_mask_UDCCR(udc, UDCCR_UDE); + udc_writel(udc, U2DICR0, 0); + udc_writel(udc, U2DICR1, 0); + //udc_writel(udc, UP2OCR, UP2OCR_HXOE); + udc_clear_mask_U2DCR(udc, U2DCR_UDE); clk_enable(udc->clk); @@ -1584,9 +1590,9 @@ static void udc_enable(struct pxa_udc *udc) udc->gadget.speed = USB_SPEED_FULL; memset(&udc->stats, 0, sizeof(udc->stats)); - udc_set_mask_UDCCR(udc, UDCCR_UDE); + udc_set_mask_U2DCR(udc, U2DCR_UDE); udelay(2); - if (udc_readl(udc, UDCCR) & UDCCR_EMCE) + if (udc_readl(udc, U2DCR) & U2DCR_EMCE) dev_err(udc->dev, "Configuration errors, udc disabled\n"); /* @@ -1595,16 +1601,16 @@ static void udc_enable(struct pxa_udc *udc) msleep(100); /* enable suspend/resume and reset irqs */ - udc_writel(udc, UDCICR1, - UDCICR1_IECC | UDCICR1_IERU - | UDCICR1_IESU | UDCICR1_IERS); + udc_writel(udc, U2DICR1, + U2DICR1_IECC | U2DICR1_IERU + | U2DICR1_IESU | U2DICR1_IERS); /* enable ep0 irqs */ pio_irq_enable(&udc->pxa_ep[0]); - dev_info(udc->dev, "UDC connecting\n"); + dev_info(udc->dev, "U2D connecting\n"); if (udc->mach->udc_command) - udc->mach->udc_command(PXA2XX_UDC_CMD_CONNECT); + udc->mach->udc_command(PXA2XX_U2D_CMD_CONNECT); } /** @@ -1623,6 +1629,8 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) struct pxa_udc *udc = the_controller; int retval; + printk("usb_gadget_register_driver\n"); + if (!driver || driver->speed != USB_SPEED_FULL || !driver->bind || !driver->disconnect || !driver->setup) return -EINVAL; @@ -1737,12 +1745,12 @@ static void handle_ep0_ctrl_req(struct pxa_udc *udc, for (i = 0; i < 2; i++) { if (unlikely(ep_is_empty(ep))) goto stall; - u.word[i] = udc_ep_readl(ep, UDCDR); + u.word[i] = udc_ep_readl(ep, U2DDR); } have_extrabytes = !ep_is_empty(ep); while (!ep_is_empty(ep)) { - i = udc_ep_readl(ep, UDCDR); + i = udc_ep_readl(ep, U2DDR); ep_err(ep, "wrong to have extra bytes for setup : 0x%08x\n", i); } @@ -1758,8 +1766,8 @@ static void handle_ep0_ctrl_req(struct pxa_udc *udc, else set_ep0state(udc, OUT_DATA_STAGE); - /* Tell UDC to enter Data Stage */ - udc_ep_writel(ep, UDCCSR, UDCCSR0_SA | UDCCSR0_OPC); + /* Tell U2D to enter Data Stage */ + udc_ep_writel(ep, U2DCSR, U2DCSR0_SA | U2DCSR0_OPC); i = udc->driver->setup(&udc->gadget, &u.r); if (i < 0) @@ -1768,8 +1776,8 @@ out: return; stall: ep_dbg(ep, "protocol STALL, udccsr0=%03x err %d\n", - udc_ep_readl(ep, UDCCSR), i); - udc_ep_writel(ep, UDCCSR, UDCCSR0_FST | UDCCSR0_FTF); + udc_ep_readl(ep, U2DCSR), i); + udc_ep_writel(ep, U2DCSR, U2DCSR0_FST | U2DCSR0_FTF); set_ep0state(udc, STALL); goto out; } @@ -1800,17 +1808,17 @@ stall: * The control endpoint state machine is _not_ USB spec compliant, it's even * hardly compliant with Intel PXA270 developers guide. * The key points which inferred this state machine are : - * - on every setup token, bit UDCCSR0_SA is raised and held until cleared by + * - on every setup token, bit U2DCSR0_SA is raised and held until cleared by * software. - * - on every OUT packet received, UDCCSR0_OPC is raised and held until + * - on every OUT packet received, U2DCSR0_OPC is raised and held until * cleared by software. - * - clearing UDCCSR0_OPC always flushes ep0. If in setup stage, never do it + * - clearing U2DCSR0_OPC always flushes ep0. If in setup stage, never do it * before reading ep0. * - irq can be called on a "packet complete" event (opc_irq=1), while - * UDCCSR0_OPC is not yet raised (delta can be as big as 100ms + * U2DCSR0_OPC is not yet raised (delta can be as big as 100ms * from experimentation). - * - as UDCCSR0_SA can be activated while in irq handling, and clearing - * UDCCSR0_OPC would flush the setup data, we almost never clear UDCCSR0_OPC + * - as U2DCSR0_SA can be activated while in irq handling, and clearing + * U2DCSR0_OPC would flush the setup data, we almost never clear U2DCSR0_OPC * => we never actually read the "status stage" packet of an IN data stage * => this is not documented in Intel documentation * - hardware as no idea of STATUS STAGE, it only handle SETUP STAGE and DATA @@ -1827,22 +1835,22 @@ static void handle_ep0(struct pxa_udc *udc, int fifo_irq, int opc_irq) struct pxa27x_request *req = NULL; int completed = 0; - udccsr0 = udc_ep_readl(ep, UDCCSR); + udccsr0 = udc_ep_readl(ep, U2DCSR); ep_dbg(ep, "state=%s, req=%p, udccsr0=0x%03x, udcbcr=%d, irq_msk=%x\n", - EP0_STNAME(udc), req, udccsr0, udc_ep_readl(ep, UDCBCR), + EP0_STNAME(udc), req, udccsr0, udc_ep_readl(ep, U2DBCR), (fifo_irq << 1 | opc_irq)); if (!list_empty(&ep->queue)) req = list_entry(ep->queue.next, struct pxa27x_request, queue); - if (udccsr0 & UDCCSR0_SST) { + if (udccsr0 & U2DCSR0_SST) { ep_dbg(ep, "clearing stall status\n"); nuke(ep, -EPIPE); - udc_ep_writel(ep, UDCCSR, UDCCSR0_SST); + udc_ep_writel(ep, U2DCSR, U2DCSR0_SST); ep0_idle(udc); } - if (udccsr0 & UDCCSR0_SA) { + if (udccsr0 & U2DCSR0_SA) { nuke(ep, 0); set_ep0state(udc, SETUP_STAGE); } @@ -1853,17 +1861,17 @@ static void handle_ep0(struct pxa_udc *udc, int fifo_irq, int opc_irq) * Hardware bug : beware, we cannot clear OPC, since we would * miss a potential OPC irq for a setup packet. * So, we only do ... nothing, and hope for a next irq with - * UDCCSR0_SA set. + * U2DCSR0_SA set. */ break; case SETUP_STAGE: - udccsr0 &= UDCCSR0_CTRL_REQ_MASK; - if (likely(udccsr0 == UDCCSR0_CTRL_REQ_MASK)) + udccsr0 &= U2DCSR0_CTRL_REQ_MASK; + if (likely(udccsr0 == U2DCSR0_CTRL_REQ_MASK)) handle_ep0_ctrl_req(udc, req); break; case IN_DATA_STAGE: /* GET_DESCRIPTOR */ if (epout_has_pkt(ep)) - udc_ep_writel(ep, UDCCSR, UDCCSR0_OPC); + udc_ep_writel(ep, U2DCSR, U2DCSR0_OPC); if (req && !ep_is_full(ep)) completed = write_ep0_fifo(ep, req); if (completed) @@ -1876,7 +1884,7 @@ static void handle_ep0(struct pxa_udc *udc, int fifo_irq, int opc_irq) ep0_end_out_req(ep, req); break; case STALL: - udc_ep_writel(ep, UDCCSR, UDCCSR0_FST); + udc_ep_writel(ep, U2DCSR, U2DCSR0_FST); break; case IN_STATUS_STAGE: /* @@ -1915,7 +1923,7 @@ static void handle_ep(struct pxa_ep *ep) do { completed = 0; - udccsr = udc_ep_readl(ep, UDCCSR); + udccsr = udc_ep_readl(ep, U2DCSR); if (likely(!list_empty(&ep->queue))) req = list_entry(ep->queue.next, struct pxa27x_request, queue); @@ -1925,9 +1933,9 @@ static void handle_ep(struct pxa_ep *ep) ep_dbg(ep, "req:%p, udccsr 0x%03x loop=%d\n", req, udccsr, loop++); - if (unlikely(udccsr & (UDCCSR_SST | UDCCSR_TRN))) - udc_ep_writel(ep, UDCCSR, - udccsr & (UDCCSR_SST | UDCCSR_TRN)); + if (unlikely(udccsr & (U2DCSR_SST | U2DCSR_TRN))) + udc_ep_writel(ep, U2DCSR, + udccsr & (U2DCSR_SST | U2DCSR_TRN)); if (!req) break; @@ -2012,30 +2020,30 @@ static void irq_handle_data(int irq, struct pxa_udc *udc) { int i; struct pxa_ep *ep; - u32 udcisr0 = udc_readl(udc, UDCISR0) & UDCCISR0_EP_MASK; - u32 udcisr1 = udc_readl(udc, UDCISR1) & UDCCISR1_EP_MASK; + u32 udcisr0 = udc_readl(udc, U2DISR0) & U2DCISR0_EP_MASK; + u32 udcisr1 = udc_readl(udc, U2DISR1) & U2DCISR1_EP_MASK; - if (udcisr0 & UDCISR_INT_MASK) { + if (udcisr0 & U2DISR_INT_MASK) { udc->pxa_ep[0].stats.irqs++; - udc_writel(udc, UDCISR0, UDCISR_INT(0, UDCISR_INT_MASK)); - handle_ep0(udc, !!(udcisr0 & UDCICR_FIFOERR), - !!(udcisr0 & UDCICR_PKTCOMPL)); + udc_writel(udc, U2DISR0, U2DISR_INT(0, U2DISR_INT_MASK)); + handle_ep0(udc, !!(udcisr0 & U2DICR_FIFOERR), + !!(udcisr0 & U2DICR_PKTCOMPL)); } udcisr0 >>= 2; for (i = 1; udcisr0 != 0 && i < 16; udcisr0 >>= 2, i++) { - if (!(udcisr0 & UDCISR_INT_MASK)) + if (!(udcisr0 & U2DISR_INT_MASK)) continue; - udc_writel(udc, UDCISR0, UDCISR_INT(i, UDCISR_INT_MASK)); + udc_writel(udc, U2DISR0, U2DISR_INT(i, U2DISR_INT_MASK)); ep = &udc->pxa_ep[i]; ep->stats.irqs++; handle_ep(ep); } for (i = 16; udcisr1 != 0 && i < 24; udcisr1 >>= 2, i++) { - udc_writel(udc, UDCISR1, UDCISR_INT(i - 16, UDCISR_INT_MASK)); - if (!(udcisr1 & UDCISR_INT_MASK)) + udc_writel(udc, U2DISR1, U2DISR_INT(i - 16, U2DISR_INT_MASK)); + if (!(udcisr1 & U2DISR_INT_MASK)) continue; ep = &udc->pxa_ep[i]; @@ -2046,12 +2054,12 @@ static void irq_handle_data(int irq, struct pxa_udc *udc) } /** - * irq_udc_suspend - Handle IRQ "UDC Suspend" + * irq_udc_suspend - Handle IRQ "U2D Suspend" * @udc: udc device */ static void irq_udc_suspend(struct pxa_udc *udc) { - udc_writel(udc, UDCISR1, UDCISR1_IRSU); + udc_writel(udc, U2DISR1, U2DISR1_IRSU); udc->stats.irqs_suspend++; if (udc->gadget.speed != USB_SPEED_UNKNOWN @@ -2061,12 +2069,12 @@ static void irq_udc_suspend(struct pxa_udc *udc) } /** - * irq_udc_resume - Handle IRQ "UDC Resume" + * irq_udc_resume - Handle IRQ "U2D Resume" * @udc: udc device */ static void irq_udc_resume(struct pxa_udc *udc) { - udc_writel(udc, UDCISR1, UDCISR1_IRRU); + udc_writel(udc, U2DISR1, U2DISR1_IRRU); udc->stats.irqs_resume++; if (udc->gadget.speed != USB_SPEED_UNKNOWN @@ -2075,44 +2083,44 @@ static void irq_udc_resume(struct pxa_udc *udc) } /** - * irq_udc_reconfig - Handle IRQ "UDC Change Configuration" + * irq_udc_reconfig - Handle IRQ "U2D Change Configuration" * @udc: udc device */ static void irq_udc_reconfig(struct pxa_udc *udc) { unsigned config, interface, alternate, config_change; - u32 udccr = udc_readl(udc, UDCCR); + u32 udccr = udc_readl(udc, U2DCR); - udc_writel(udc, UDCISR1, UDCISR1_IRCC); + udc_writel(udc, U2DISR1, U2DISR1_IRCC); udc->stats.irqs_reconfig++; - config = (udccr & UDCCR_ACN) >> UDCCR_ACN_S; + config = (udccr & U2DCR_ACN) >> U2DCR_ACN_S; config_change = (config != udc->config); pxa27x_change_configuration(udc, config); - interface = (udccr & UDCCR_AIN) >> UDCCR_AIN_S; - alternate = (udccr & UDCCR_AAISN) >> UDCCR_AAISN_S; + interface = (udccr & U2DCR_AIN) >> U2DCR_AIN_S; + alternate = (udccr & U2DCR_AAISN) >> U2DCR_AAISN_S; pxa27x_change_interface(udc, interface, alternate); if (config_change) update_pxa_ep_matches(udc); - udc_set_mask_UDCCR(udc, UDCCR_SMAC); + udc_set_mask_U2DCR(udc, U2DCR_SMAC); } /** - * irq_udc_reset - Handle IRQ "UDC Reset" + * irq_udc_reset - Handle IRQ "U2D Reset" * @udc: udc device */ static void irq_udc_reset(struct pxa_udc *udc) { - u32 udccr = udc_readl(udc, UDCCR); + u32 udccr = udc_readl(udc, U2DCR); struct pxa_ep *ep = &udc->pxa_ep[0]; dev_info(udc->dev, "USB reset\n"); - udc_writel(udc, UDCISR1, UDCISR1_IRRS); + udc_writel(udc, U2DISR1, U2DISR1_IRRS); udc->stats.irqs_reset++; - if ((udccr & UDCCR_UDA) == 0) { + if ((udccr & U2DCR_UDA) == 0) { dev_dbg(udc->dev, "USB reset start\n"); stop_activity(udc, udc->driver); } @@ -2120,7 +2128,7 @@ static void irq_udc_reset(struct pxa_udc *udc) memset(&udc->stats, 0, sizeof udc->stats); nuke(ep, -EPROTO); - udc_ep_writel(ep, UDCCSR, UDCCSR0_FTF | UDCCSR0_OPC); + udc_ep_writel(ep, U2DCSR, U2DCSR0_FTF | U2DCSR0_OPC); ep0_idle(udc); } @@ -2134,25 +2142,25 @@ static void irq_udc_reset(struct pxa_udc *udc) static irqreturn_t pxa_udc_irq(int irq, void *_dev) { struct pxa_udc *udc = _dev; - u32 udcisr0 = udc_readl(udc, UDCISR0); - u32 udcisr1 = udc_readl(udc, UDCISR1); - u32 udccr = udc_readl(udc, UDCCR); + u32 udcisr0 = udc_readl(udc, U2DISR0); + u32 udcisr1 = udc_readl(udc, U2DISR1); + u32 udccr = udc_readl(udc, U2DCR); u32 udcisr1_spec; - dev_vdbg(udc->dev, "Interrupt, UDCISR0:0x%08x, UDCISR1:0x%08x, " - "UDCCR:0x%08x\n", udcisr0, udcisr1, udccr); + dev_vdbg(udc->dev, "Interrupt, U2DISR0:0x%08x, U2DISR1:0x%08x, " + "U2DCR:0x%08x\n", udcisr0, udcisr1, udccr); udcisr1_spec = udcisr1 & 0xf8000000; - if (unlikely(udcisr1_spec & UDCISR1_IRSU)) + if (unlikely(udcisr1_spec & U2DISR1_IRSU)) irq_udc_suspend(udc); - if (unlikely(udcisr1_spec & UDCISR1_IRRU)) + if (unlikely(udcisr1_spec & U2DISR1_IRRU)) irq_udc_resume(udc); - if (unlikely(udcisr1_spec & UDCISR1_IRCC)) + if (unlikely(udcisr1_spec & U2DISR1_IRCC)) irq_udc_reconfig(udc); - if (unlikely(udcisr1_spec & UDCISR1_IRRS)) + if (unlikely(udcisr1_spec & U2DISR1_IRRS)) irq_udc_reset(udc); - if ((udcisr0 & UDCCISR0_EP_MASK) | (udcisr1 & UDCCISR1_EP_MASK)) + if ((udcisr0 & U2DCISR0_EP_MASK) | (udcisr1 & U2DCISR1_EP_MASK)) irq_handle_data(irq, udc); return IRQ_HANDLED; @@ -2217,6 +2225,7 @@ static int __init pxa_udc_probe(struct platform_device *pdev) struct resource *regs; struct pxa_udc *udc = &memory; int retval; + printk("pxa27x_udc probe\n"); regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!regs) @@ -2228,16 +2237,18 @@ static int __init pxa_udc_probe(struct platform_device *pdev) udc->dev = &pdev->dev; udc->mach = pdev->dev.platform_data; - udc->clk = clk_get(&pdev->dev, "UDCCLK"); + udc->clk = clk_get(&pdev->dev, "U2DCLK"); if (IS_ERR(udc->clk)) { retval = PTR_ERR(udc->clk); + printk("clock error\n"); goto err_clk; } retval = -ENOMEM; udc->regs = ioremap(regs->start, regs->end - regs->start + 1); if (!udc->regs) { - dev_err(&pdev->dev, "Unable to map UDC I/O memory\n"); + dev_err(&pdev->dev, "Unable to map U2D I/O memory\n"); + printk("udc mmap error\n"); goto err_map; } @@ -2260,6 +2271,7 @@ static int __init pxa_udc_probe(struct platform_device *pdev) } pxa_init_debugfs(udc); + printk("pxa27x_udc_probe done\n"); return 0; err_irq: iounmap(udc->regs); @@ -2293,7 +2305,7 @@ static void pxa_udc_shutdown(struct platform_device *_dev) { struct pxa_udc *udc = platform_get_drvdata(_dev); - if (udc_readl(udc, UDCCR) & UDCCR_UDE) + if (udc_readl(udc, U2DCR) & U2DCR_UDE) udc_disable(udc); } @@ -2303,7 +2315,7 @@ static void pxa_udc_shutdown(struct platform_device *_dev) * @_dev: platform device * @state: suspend state * - * Suspends udc : saves configuration registers (UDCCR*), then disables the udc + * Suspends udc : saves configuration registers (U2DCR*), then disables the udc * device. */ static int pxa_udc_suspend(struct platform_device *_dev, pm_message_t state) @@ -2313,11 +2325,11 @@ static int pxa_udc_suspend(struct platform_device *_dev, pm_message_t state) struct pxa_ep *ep; ep = &udc->pxa_ep[0]; - udc->udccsr0 = udc_ep_readl(ep, UDCCSR); + udc->udccsr0 = udc_ep_readl(ep, U2DCSR); for (i = 1; i < NR_PXA_ENDPOINTS; i++) { ep = &udc->pxa_ep[i]; - ep->udccsr_value = udc_ep_readl(ep, UDCCSR); - ep->udccr_value = udc_ep_readl(ep, UDCCR); + ep->udccsr_value = udc_ep_readl(ep, U2DCSR); + ep->udccr_value = udc_ep_readl(ep, U2DCR); ep_dbg(ep, "udccsr:0x%03x, udccr:0x%x\n", ep->udccsr_value, ep->udccr_value); } @@ -2331,7 +2343,7 @@ static int pxa_udc_suspend(struct platform_device *_dev, pm_message_t state) * pxa_udc_resume - Resume udc device * @_dev: platform device * - * Resumes udc : restores configuration registers (UDCCR*), then enables the udc + * Resumes udc : restores configuration registers (U2DCR*), then enables the udc * device. */ static int pxa_udc_resume(struct platform_device *_dev) @@ -2341,11 +2353,11 @@ static int pxa_udc_resume(struct platform_device *_dev) struct pxa_ep *ep; ep = &udc->pxa_ep[0]; - udc_ep_writel(ep, UDCCSR, udc->udccsr0 & (UDCCSR0_FST | UDCCSR0_DME)); + udc_ep_writel(ep, U2DCSR, udc->udccsr0 & (U2DCSR0_FST | U2DCSR0_DME)); for (i = 1; i < NR_PXA_ENDPOINTS; i++) { ep = &udc->pxa_ep[i]; - udc_ep_writel(ep, UDCCSR, ep->udccsr_value); - udc_ep_writel(ep, UDCCR, ep->udccr_value); + udc_ep_writel(ep, U2DCSR, ep->udccsr_value); + udc_ep_writel(ep, U2DCR, ep->udccr_value); ep_dbg(ep, "udccsr:0x%03x, udccr:0x%x\n", ep->udccsr_value, ep->udccr_value); } @@ -2357,11 +2369,12 @@ static int pxa_udc_resume(struct platform_device *_dev) * OTGPH bit is set when sleep mode is entered. * it indicates that OTG pad is retaining its state. * Upon exit from sleep mode and before clearing OTGPH, - * Software must configure the USB OTG pad, UDC, and UHC + * Software must configure the USB OTG pad, U2D, and UHC * to the state they were in before entering sleep mode. */ - if (cpu_is_pxa27x()) - PSSR |= PSSR_OTGPH; + //if (cpu_is_pxa27x()) +// PSSR |= PSSR_OTGPH; +//err... return 0; } @@ -2385,8 +2398,8 @@ static struct platform_driver udc_driver = { static int __init udc_init(void) { - if (!cpu_is_pxa27x()) - return -ENODEV; + //if (!cpu_is_pxa27x()) + // return -ENODEV; printk(KERN_INFO "%s: version %s\n", driver_name, DRIVER_VERSION); return platform_driver_probe(&udc_driver, pxa_udc_probe); -- 1.5.4.3